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M34C02
2 Kbit Serial IC Bus EEPROM For DIMM Serial Presence Detect
s
Two Wire I2C Serial Interface Supports 400 kHz Protocol Single Supply Voltage: - 2.5V to 5.5V for M34C02-W - 2.2V to 5.5V for M34C02-L
s
8 1
PSDIP8 (BN) 0.25 mm frame
s s s s s s s s
Software Data Protection for lower 128 bytes BYTE and PAGE WRITE (up to 16 bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection 1 Million Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
8 1
SO8 (MN) 150 mil width
8 1
TSSOP8 (DW) 169 mil width
DESCRIPTION The M34C02 is a 2 Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. This bottom half of the memory area can be writeprotected using a specially designed software write protection mechanism. By sending the device a specific sequence, the first 128 bytes of Table 1. Signal Names
E0, E1, E2 SDA Chip Enable Inputs
Figure 1. Logic Diagram
VCC
3 E0-E2 SCL
Serial Data/Address Input/ Output Serial Clock Write Control Supply Voltage Ground
SDA M34C02
WC
SCL WC VCC VSS
VSS
AI01931
December 1999
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M34C02
Figure 2A. DIP Connections Figure 2B. SO and TSSOP Connections
M34C02 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01932
M34C02 VCC WC SCL SDA E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI01933
VCC WC SCL SDA
the memory become permanently write protected. Care must be taken when using this sequence as its effect cannot be reversed. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to V CC). The M34C02 is a 2 Kbit electrically erasable programmable memory (EEPROM), organized as 256x8 bits, fabricated with STMicroelectronics' High Endurance, Advanced, CMOS technology. This guarantees an endurance typically well above one million Erase/Write cycles, with a data retention of 40 years. These memory devices operate with a power supply down to 2.2 V for the M34C02-L. The M34C02 is available in Plastic Dual In-line, Plastic Small Outline and Thin Shrink Small Outline packages. These memory devices are compatible with the I2C memory standard. This is a two wire serial Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage
interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second Device Type Identifier Code (0110) to access the Protection Register. These codes are used together with three chip enable inputs (E2, E1, E0) so that up to eight 2 Kbit devices may be attached to the IC bus and selected individually. The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission.
Value -40 to 85 -65 to 150 PSDIP8: 10 sec SO8: 40 sec TSSOP8: 40 sec 260 215 215 -0.6 to 6.5 -0.3 to 6.5 4000
Unit C C C V V V
Electrostatic Discharge Voltage (Human Body model) 2
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
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M34C02
When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The internal reset is held active until the V CC voltage has reached the POR threshold value, and all operations are disabled - the device will not respond to any command. In the same way, when V CC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid VCC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) The SCL input pin is used to strobe all data in and out of the memory. In applications where this line is used by slaves to synchronize the bus to a slower clock, the master must have an open drain output, and a pull-up resistor must be connected from the SCL line to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the master has a push-pull (rather than open drain) output. Serial Data (SDA) The SDA pin is bi-directional, and is used to transfer data in or out of the memory. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from the SDA bus to V CC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E2, E1, E0) These chip enable inputs are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs may be driven dynamically or tied to VCC or VSS to establish the device select code. Write Control (WC) A hardware Write Control (WC, pin 7) is provided for protecting the contents of the whole memory from erroneous erase/write cycles. The Write Control signal is used to enable (WC=V IL) or disable (WC=VIH) write instructions to the entire memory area or to the Protection Register. When WC is tied to V SS or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register. DEVICE OPERATION The memory device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the master, and the other as the slave. A data transfer can only be initiated by the master, which will also provide the serial clock for synchronization. The memory device is always a slave device in all communication.
Figure 3. Maximum R L Value versus Bus Capacitance (CBUS) for an I2C Bus
VCC 20 Maximum RP value (k) 16 RL 12 8 4 0 10 100 CBUS (pF)
AI01665
RL
SDA MASTER fc = 100kHz fc = 400kHz SCL CBUS
CBUS 1000
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M34C02
Figure 4. I2C Bus Protocol
SCL
SDA START CONDITION SDA INPUT SDA CHANGE STOP CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
START CONDITION
SCL
1
2
3
7
8
9
SDA
MSB
ACK
STOP CONDITION
AI00792
Start Condition START is identified by a high to low transition of the SDA line while the clock, SCL, is stable in the high state. A START condition must precede any data transfer command. The memory device continuously monitors (except during a programming cycle) the SDA and SCL lines for a START condition, and will not respond unless one is given.
Stop Condition STOP is identified by a low to high transition of the SDA line while the clock SCL is stable in the high state. A STOP condition terminates communication between the memory device and the bus master. A STOP condition at the end of a Read command, provided that it is followed by a NoAck, forces the memory device into its standby state. A STOP condition at the end of a Write
Table 3. Device Select Code 1
Device Type Identifier b7 Memory Area Select Code (two arrays) Protection Register Select Code
Note: 1. The most significant bit (b7) is sent first.
Chip Enable b4 0 0 b3 E2 E2 b2 E1 E1 b1 E0 E0
RW b0 RW RW
b6 0 1
b5 1 1
1 0
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M34C02
Table 4. Operating Modes
Mode Current Address Read Random Address Read 1 Sequential Read Byte Write Page Write
Note: 1. X = VIH or VIL.
RW bit 1 0
WC 1 X X
Bytes 1 1
Initial Sequence START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1'
X X VIL VIL 1 1 16
1 0 0
Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0'
command triggers the internal EEPROM write cycle. Acknowledge Bit (ACK) An acknowledge signal is used to indicate a successful byte transfer. The bus transmitter, whether it be master or slave, releases the SDA bus after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA bus low to acknowledge the receipt of the eight data bits. Data Input During data input, the memory device samples the SDA bus signal on the rising edge of the clock, SCL. For correct device operation, the SDA signal must be stable during the clock low-to-high transition, and the data must change only when the SCL line is low. Memory Addressing To start communication between the bus master and the slave memory, the master must initiate a START condition. Following this, the master sends the 8-bit byte, shown in Table 3, on the SDA bus line (most significant bit first). This consists of the 7-bit Device Select Code, and the 1-bit Read/Write Designator (RW). The Device Select Code is further subdivided into: a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b. To address the Protection Register, it is 0110b. If all three chip enable inputs are connected, up to eight memory devices can be connected on a single I 2C bus. Each one is given a unique 3-bit code on its Chip Enable inputs. When the Device Select Code is received on the SDA bus, the memory only responds if the Chip Select Code is the same as the pattern applied to its Chip Enable pins. The 8th bit is the read or write bit (RW). This bit is set to `1' for read and `0' for write operations. If a
match occurs on the Device Select Code, the corresponding memory gives an acknowledgment on the SDA bus during the 9 th bit time. If the memory does not match the Device Select code, it will deselect itself from the bus, and go into standby mode. Write Operations Following a START condition the master sends a Device Select Code with the RW bit set to '0', as shown in Table 4. The memory acknowledges this, and waits for an address byte. The memory responds to the address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the WC input pin is taken high. Byte Write In the Byte Write mode, after the Device Select Code and the address byte, the master sends one data byte. If the addressed location is in a write protected area, the memory replies with a NoAck, and the location is not modified. If, instead, the addressed location is not in a write protected area, the memory replies with an Ack. The master terminates the transfer by generating a STOP condition. Page Write The Page Write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same 'row' in the memory: that is the most significant memory address bits (b7-b4) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. Data starts to become overwritten (in a way not formally specified in this data sheet). The master sends from one up to 16 bytes of data, each of which is acknowledged by the memory if the WC pin is low. If the WC pin is high, the contents of the addressed memory location are not modified. After each byte is transferred, the internal byte address counter (the 4 least
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M34C02
Figure 5. How to Set the Write Protection
FFh Standard Array Memory Area Standard Array 00h Default EEPROM memory area state before write access to the Protect Register 80h 7Fh Standard Array Write Protected Array
FFh
80h 7Fh
00h
State of the EEPROM memory area after write access to the Protect Register
AI01936C
Figure 6. Write Mode Sequences in the Non Write-Protected Area
ACK BYTE WRITE START DEV SEL R/W ACK PAGE WRITE START DEV SEL R/W ACK DATA IN N STOP ACK ACK DATA IN 1 ACK DATA IN STOP ACK DATA IN 2 BYTE ADDR
AI01941
ACK
BYTE ADDR
significant bits only) is incremented. The transfer is terminated by the master generating a STOP condition. When the master generates a STOP condition immediately after the Ack bit (in the "10 th bit" time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. A STOP condition at any other time does not trigger the internal write cycle. During the internal write cycle, the SDA input is disabled internally, and the device does not respond to any requests.
Minimizing System Delays by Polling On ACK During the internal write cycle, the memory disconnects itself from the bus, and copies the data from its internal latches to the memory cells. The maximum write time (tw) is shown in Table 9, but the typical time is shorter. To make use of this, an Ack polling sequence can be used by the master.
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M34C02
Figure 7. Write Cycle Polling Flowchart using ACK
WRITE Cycle in Progress
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by M34C02
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Byte Address
STOP
Proceed WRITE Operation
Proceed Random Address READ Operation
AI01934
Figure 8. Setting the Write Protection Register (WC = 0)
START BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY ACK ACK ACK CONTROL BYTE WORD ADDRESS STOP
AI01935
DATA
VALUE DON'T CARE
VALUE DON'T CARE
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M34C02
The sequence, as shown in Figure 7, is: - Initial condition: a Write is in progress. - Step 1: the master issues a START condition followed by a Device Select Code (the first byte of the new instruction). - Step 2: if the memory is busy with the internal write cycle, no Ack will be returned and the master goes back to Step 1. If the memory has terminated the internal write cycle, it responds with an Ack, indicating that the memory is ready to receive the second part of the next instruction (the first byte of this instruction having been sent during Step 1). Setting the Protection, Using the Protection Register The M34C02 has a software write-protection function, using the Protecton Register, that allows the bottom half of the memory area (addresses 00h to 7Fh) to be permanently write protected. The write protection feature is activated by writing once to the Protection Register (with the WC input held at VSS). The Protection Register is accessed with the device select code set to 0110b (as shown in Table 3), and the E2-E1-E0 bits set according to the states being applied to the E2-E1-E0 pins. As
Figure 9. Read Mode Sequences
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP ACK DEV SEL * START R/W
ACK RANDOM ADDRESS READ START DEV SEL * R/W
ACK
NO ACK DATA OUT STOP NO ACK ACK
AI01942
BYTE ADDR
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W
ACK
ACK
DATA OUT 1
DATA OUT N STOP
ACK SEQUENTIAL RANDOM READ START DEV SEL * R/W
ACK DEV SEL * START
ACK
BYTE ADDR
DATA OUT 1 R/W
ACK
NO ACK
DATA OUT N STOP
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 st and 3rd bytes) must be identical.
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M34C02
for any other write command, the WC input needs to be held at V SS. Address and data bytes must be sent with this command, but their values are all ignored, and are treated as Don't Care. Once the Protection Register has been written, the write protection of the first 128 bytes of the memory is enabled, and it is not possible to unprotect these 128 bytes, even if the device is powered off and on, and regardless the state of the WC input. When the Protection Register has been written, the M34C02 no longer responds to the device type identifier 0110b in either read or write mode. Read Operations Read operations are performed independently of the state of the WC pin. Random Address Read A dummy write is performed to load the address into the address counter, as shown in Figure 9. Then, without sending a STOP condition, the master sends another START condition, and repeats the Device Select Code, with the RW bit set to `1'. The memory acknowledges this, and outputs the contents of the addressed byte. The master must not acknowledge the byte output, and terminates the transfer with a STOP condition. Current Address Read The device has an internal address counter which is incremented each time a byte is read. For the Current Address Read mode, following a START condition, the master sends a Device Select Code with the RW bit set to `1'. The memory acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The master terminates the transfer with a STOP condition, as shown in Figure 9, without acknowledging the byte output. Sequential Read This mode can be initiated with either a Current Address Read or a Random Address Read. The master does acknowledge the data byte output in this case, and the memory continues to output the next byte in sequence. To terminate the stream of bytes, the master must not acknowledge the last byte output, and must generate a STOP condition. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over' and the memory continues to output data from address 00h (at the start of the memory block). Acknowledge in Read Mode In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9th bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its standby state. USE WITHIN A DRAM DIMM In the application, the M34C02 is soldered directly in the printed circuit module. The 3 Chip Enable inputs (pins 1, 2 and 3) are connected to pins 165, 166 and 167, respectively, of the 168-pin DRAM DIMM module. They are wired at VCC or VSS through the DIMM socket (see Table 5). The SCL and SDA lines (pins 6 and 5) are connected respectively to pins 83 and 82 of the memory module. The pull-up resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the mother-board (as shown in Figure 10). The Write Control input of the M34C02 (WC on pin 7) can be left unconnected. However, connecting it to V SS is recommended, to maintain full read and write access to the top half of the memory. Programming the M34C02 When the M34C02 is delivered, full read and write access is given to the whole memory array. It is recommended that the first step is to use the test equipment to write the module information (such as its access speed, its size, its organization) to the first half of the memory, starting from the first memory location. When the data has been validated, the test equipment can send a Write command to the Protection Register, using the device select code '01100000b' followed by an address and data byte (made up of Don't Care values) as shown in Figure 8. The first 128 bytes of the memory area are then write-protected, and the M34C02 will no longer respond to the specific device select code '0110000xb'. It is not possible to reverse this sequence.
Table 5. 168 Pin DRAM DIMM Connections
DIMM Position 0 1 2 3 4 5 6 7 E2 (pin 167) VSS VSS VSS VSS VCC VCC VCC VCC E1 (pin 166) VSS VSS VCC VCC VSS VSS VCC VCC E0 (pin 165) VSS VCC VSS VCC VSS VCC VSS VCC
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M34C02
Figure 10. Serial Presence Detect Block Diagram
DIMM Position 7 E2 E1 E0 SCL SDA
R = 4.7k
VCC DIMM Position 6 E2 E1 E0 SCL SDA
VCC DIMM Position 5 E2 E1
VSS
E0
SCL SDA
VCC VSS VCC DIMM Position 4 E2 E1 E0 SCL SDA
VCC DIMM Position 3 E2 E1
VSS
E0
SCL SDA
VSS DIMM Position 2 E2 E1
VCC
E0
SCL SDA
VSS VCC VSS DIMM Position 1 E2 E1 E0 SCL SDA
VSS DIMM Position 0 E2 E1
VCC
E0
SCL SDA
VSS
SCL line
AI01937
SDA line
From the motherboard I2C master controller
Note: 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices. 3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 k) because these lines are open drain when used as outputs.
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M34C02
Table 6. DC Characteristics (TA = -40 to 85 C; VCC = 2.5 to 5.5 V, 2.2 to 5.5 V)
Symbol ILI ILO Parameter Input Leakage Current SCL, SDA Test Condition 0 V VIN VCC 0 V VOUT VCC, SDA in Hi-Z VCC =5V, fc=400kHz (rise/fall time < 30ns) Min. Max. 2 2 2 1 1 1 0.5 0.5 - 0.3 - 0.3 - 0.3 0.7VCC 0.7VCC 0.7VCC IOL = 3 mA, VCC = 5 V IOL = 2.1 mA, VCC = 2.5 V IOL = 2.1 mA, VCC = 2.2 V 0.3VCC 0.3VCC 0.5 VCC+1 VCC+1 VCC+1 0.4 0.4 0.4 Unit A A mA mA mA A A A V V V V V V V V V
Output Leakage Current -W or -L series
ICC
Supply Current
-W series VCC =2.5V, fc=400kHz (rise/fall time < 30ns) -L series VCC =2.2V, fc=400kHz (rise/fall time < 30ns) -W or -L series VIN = VSS or VCC , VCC = 5 V VIN = VSS or VCC , VCC = 2.5 V VIN = VSS or VCC , VCC = 2.2 V
ICC1
Supply Current (Stand-by)
-W series -L series SCL, SDA
VIL
Input Low Voltage
E0, E1, E2 WC SCL, SDA
VIH
Input High Voltage
E0, E1, E2 WC -W or -L series
VOL
Output Low Voltage
-W series -L series
Table 7. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages 50 ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC
Figure 11. AC Testing Input Output Waveforms
0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
Table 8. Input Parameters 1(T A = 25 C, f = 400 kHz)
Symbol CIN CIN ZWCL ZWCH tNS Parameter Input Capacitance (SDA) Input Capacitance (other pins) WC Input Impedance WC Input Impedance Low Pass Filter Input Time Constant (SCL and SDA) VIN < 0.5 V VIN > 0.7VCC 5 500 100 500 Test Condition Min. Max. 8 6 20 Unit pF pF k k ns
Note: 1. Sampled only, not 100% tested.
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M34C02
Table 9. AC Characteristics
M34C02-W Symbol Alt. Parameter VCC=2.5 to 5.5V TA = -40 to 85C Min tCH1CH2 tCL1CL2 tDH1DH2 2 tDL1DL2 2 tCHDX 1 tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV
3
M34C02-L VCC=2.2 to 5.5V TA = -40 to 85C Min Max 300 300 20 20 600 600 600 0 1.3 100 600 1.3 300 300 ns ns ns ns ns ns ns s s ns ns s 900 ns ns 400 10 kHz ms Unit
Max 300 300
tR tF tR tF tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF tAA tDH fSCL tWR
Clock Rise Time Clock Fall Time SDA Rise Time SDA Fall Time Clock High to Input Transition Clock Pulse Width High Input Low to Clock Low (START) Clock Low to Input Transition Clock Pulse Width Low Input Transition to Clock Transition Clock High to Input High (STOP) Input High to Input Low (Bus Free) Clock Low to Data Out Valid Data Out Hold Time After Clock Low Clock Frequency Write Time 20 20 600 600 600 0 1.3 100 600 1.3 200 200
300 300
900
200 200
tCLQX fC tW
400 10
Note: 1. For a reSTART condition, or following a write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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M34C02
Figure 12. AC Waveforms
tCHCL SCL tDLCL SDA IN tCHDX START CONDITION tCLDX SDA INPUT SDA CHANGE STOP & BUS FREE tDHDL tDXCX tCHDH tCLCH
SCL tCLQV SDA OUT DATA VALID tCLQX
DATA OUTPUT
SCL tW SDA IN tCHDH STOP CONDITION WRITE CYCLE tCHDX START CONDITION
AI00795B
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M34C02
Table 10. Ordering Information Scheme
Example: M34C02 -W MN 6 T
Operating Voltage W L 2.5 V to 5.5 V 2.2 V to 5.5 V T
Option Tape and Reel Packing
Package BN1 MN DW PSDIP8 (0.25 mm frame) SO8 (150 mil width) TSSOP8 (169 mil width) 6
Temperature Range -40 C to 85 C
Note: 1. Package-type available only on request.
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh), and the Protection Register set at all `0's (00h).
The notation used for the device number is as shown in Table 10. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M34C02
Table 11. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA eB L N 3.00 8 2.54 7.62 Min. 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max. 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.100 0.300 Typ. Min. 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max. 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150 inches
Figure 13. PSDIP8 (BN)
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Note: 1. Drawing is not to scale.
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M34C02
Table 12. SO8 - 8 lead Plastic Small Outline, 150 mils body width
mm Symb. Typ. A A1 B C D E e H h L N CP 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8 inches
Figure 14. SO8 narrow (MN)
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Note: 1. Drawing is not to scale.
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M34C02
Table 13. TSSOP8 - 8 lead Thin Shrink Small Outline
mm Symb. Typ. A A1 A2 B C D E E1 e L N CP 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 - 0.50 0 8 0.08 Min. Max. 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 - 0.70 8 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 - 0.020 0 8 0.003 Typ. Min. Max. 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 - 0.028 8 inches
Figure 15. TSSOP8 (DW)
D
N
DIE
C
E1 E
1
N/2
A1
A A2
L
CP
B
e TSSOP
Note: 1. Drawing is not to scale.
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M34C02
Table 14. Revision History
Date 27-Dec-1999 Description of Revision Adjustments to the formatting. 0 to 70C temperature range removed from DC and AC tables. No change to description of device, or parameters
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M34C02
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) 1999 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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Price & Availability of M34C02

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